Hardware Info

Registers

AddressNameDescriptionBits
4000S_SQR1_Att_c_d_vvvv t=duty type, c=decay_looping/length, d=decay disable, v=volume/decay_rate
4001S_SQR1_Be_rrr_o_sss e=sweep enable, r=sweep rate, o=decrease/increase, s=right shift amount
4002S_SQR1_Cwwwwwwww LSB of wavelength
4003S_SQR1_Dnnnnn_xxx n=length counter reload, x=MSB of wavelength
4004S_SQR2_Att_c_d_vvvv t=duty type, c=decay_looping/length, d=decay disable, v=volume/decay_rate
4005S_SQR2_Be_rrr_o_sss e=sweep enable, r=sweep rate, o=decrease/increase, s=right shift amount
4006S_SQR2_Cwwwwwwww LSB of wavelength
4007S_SQR2_Dnnnnn_xxx n=length counter reload, x=MSB of wavelength
4008S_TRI_Ac_aaaaaaa c=linear counter start, a=linear counter load
4009S_TRI_B++++++++ unused
400AS_TRI_Cwwwwwwww LSB of wavelength
400BS_TRI_Dnnnnn_xxx n=length counter reload, x=MSB of wavelength
400CS_NOI_A++_c_d_vvvv c=decay_looping/length, d=decay disable, v=volume/decay_rate
400DS_NOI_B++++++++ unused
400ES_NOI_Cg_+++_pppp g=random generation type, p=playback rate
400FS_NOI_Dnnnnn_xxx n=length counter reload, x=MSB of wavelength
4010S_DMC_Amm_++_ffff m=mode, f=frequency
4011S_DMC_B+_vvvvvv_d v=load value of delta counter, d=LSB of DAC
4012S_DMC_Caaaaaaaa DMA start address (shl 6)
4013S_DMC_Dcccccccc Length of DMA data (shl 4)
4014P_SPR_DMA
4015S_Statusi_q_+_d_ntba i=IRQ(ro) status,q=DMC status, d=DMC, ntba=noise/triangle/square2/square1
40164016
4017S_FrameCntrd_s_++++++ d=divider rate, s=frame counter status
2000P_CNTRL_1n+sbiaa
2001P_CNTRL_2
2002P_STATUS
2003P_SPR_ADDRdestination address for port 2004 and 4014 (incremented with write ... not read)
2004P_SPR_DATAread/write data
2005P_BKG_SCROLL
2006P_VRAM_ADDR
2007P_VRAM_DATA

Mapper 1: MMC1

TODO: These should be "w"

8000:9FFF MMC1_0
A000:BFFFMMC1_1
C000:EFFFMMC1_2
E000:FFFFMMC1_3

The Legend of Zelda uses the MMC1 chip to map the RAM/ROM banks for the CPU and PPU. MMC1 is controlled by writing to 8000-FFFF (assumes that this area is ROM where writes have no effect). There are 4 5-bit registers in the MMC1. Writing to 8000-9FFF sends data to register 0. A000-BFFF writes to register 1, C000-DFFF to register 2, and E000-FFFF to register 3.

The MMC1 register data is shifted in with 5 consecutive writes. Bit 0 of the written value goes to bit-0 on the first write then bit-1 on the second. After 5 the bit-pointer goes back to bit-0. If bit 7 of the written value is 1 then the 5-bit register is cleared and the pointer goes back to bit-0 for the NEXT write.